Sequential-access memory

ABSTRACT

A sequential-access memory of an auto-refreshing type has an increased storage capacity. The sequential-access memory has at least two dynamic-type memory cell arrays serially connected to one another to form a loop. Each array comprises N rows by M columns of memory cells each having a read selection line and a write selection line. The read selection line of each memory cell of each row is connected to the write selection line of the memory cell of the same row which comes next to the each memory cell to form an address selection line. The address selection lines of each memory cell array are activated one after another to effect a sequential access to the memory cell array. Data read form each memory cell array is fed through a delay circuit to the memory cell array which comes next to the each memory cell array. A logic circuit for subjecting data outputted from one memory array may be additionally provided to feed data representative of the result of the predetermined operation to the next memory array.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a memory of a sequential access type and moreparticularly to such a sequential-access memory which is automaticallyrefreshed and has an increased memory capacity.

2. Related Art

There have been proposed various kinds of sequential-access memories ofdynamic types which are, in general, suitable for storing musical datasuch as tone pitch data and tone color data for electronic musicalinstruments.

One of the inventors of the present application has proposed asequential-access memory of such kind in Japanese Patent Application No.58-214898 which was laid-open under No. 60-107795. FIG. 1 shows thestructure of the sequential-access memory 10 which is arrange to store"n" pieces of bits. (Four memories 10 connected in parallel are shown inFIG. 1.) In FIG. 1, shown at 11₁ to 11_(n) are a row of conventionalthree-transistor type dynamic RAM storage cells each of which comprisesthree transistors T3 to T5 and a capacitor C. The transistor T4cooperates with the capacitor C to form an information storage element.More specifically, the transistor T4 conducts when the capacitor C ischarged, and is off when the capacitor C is discharged. When a gate ofthe transistor T5 of the cell 11_(i) ("i" is any one of "1" to "n"),that is, a read selection line R_(i) of the cell 11_(i), is suppliedwith a selection signal S_(i) of "1", the transistor T5 of the cell11_(i) conducts to connect the transistor T4 of the cell 11_(i) to aread data line 12. The read selection line R_(i) of the cell 11_(i) isconnected to a gate of the transistor T3 of the preceding stage cell11_(i-1), that is, a write selection line W_(i-1) of the preceding stagecell 11_(i-1). When a gate of the transistor T3 of the cell 11_(i), thatis, a write selection line W_(i) of the cell _(i), is supplied with aselection signal S_(i+1) of "1", the transistor T3 of the cell 11_(i)conducts to connect a data write line 13 to the capacitor C of the cell11_(i), whereby the capacitor C is charged or discharged in accordancewith a signal on the data write line 13. The write selection line W_(i)of the cell 11_(i) is connected to the read selection line R_(i+1) ofthe succeeding stage cell 11_(i+1).

Thus, the dynamic storage cells 11₁ to 11_(n) are serially connected insuch a manner that the read selection line R_(i) of the cell 11_(i) isconnected to the write selection line W_(i-1) of the preceding stagecell 11_(i-1). All the cells 11₁ to 11_(n) are connected to the commonread data line 12 and to the common write data line 13. The memory 10 isdriven by a pair of clock signals φ1 and φ2 180° out of phase from eachother (see FIGS. 2-(a) and 2-(b)), each clock having a period of T. Theselection signals S₁ to S_(n) are rendered "1" one after another insynchronism with the clock signal φ2 to achieve a sequential access tothe cells 11₁ to 11_(n), as shown in FIG. 2.

In operation, when the selection signal S₁ (FIG. 2-(d)) is rendered "1"to access the storage cell 11₁, the data contained in the cell 11₁ isoutputted onto the read data line 12 as read data DR₁ and stored into alatch 14 by the clock signal φ2 (FIG. 2-(b)). The data DR₁ thus readfrom the cell 11₁ and stored in the latch 14 is inverted by an inverter15 and outputted from this memory 10 as an output data OUT1 (FIG.2-(h)). If a write pulse signal W (FIG. 2-(k)) is at the "0" level atthis time, the output data OUT1 is also fed through a selector 16 to adelay circuit 17 and stored thereinto by the clock signal φ1 (FIG.2-(a)). The data OUT1 (or the data DR₁) thus stored into the delaycircuit 17 is outputted therefrom onto the write data line 13 by thenext clock φ2. The next selection signal S₂ is rendered "1"simultaneously with this clock signal φ2, so that the data outputtedonto the write data line 13, which is the same data as the data DR₁ readfrom the cell 11₁, is written into the same cell 11₁, thereby the cell11₁ being refreshed. If the write pulse signal W is at the "1" level,write data DW₁ (FIG. 2-(j)) from the exterior passes through theselector 16 and is stored into the delay circuit 17, so that the newdata DW₁ is written into the cell 11₁. The data on the write data line13 is also outputted from this memory 10 as data OUT2 (FIG. 2-(i)). Theoperation is true of the cells 11₂ to 11_(n). The read data line 12 ispre-charged immediately before each reading operation through atransistor 18 which is conducted by a pre-charge control pulse signal PC(FIG. 2-(c)) generated in synchronization with the clock signal φ1.

With the above arrangement, all the memory cells 11₁ to 11_(n) of thememory 10 are sequentially accessed and are therefore automaticallyrefreshed. In addition, the memory 10 has a function to delay each databy a time period corresponding to "n" cycles of the clock signal φ1, φ2.However, the memory 10 is not satisfactory in the following respects:

When the number "n" of storage cells is augmented to increase thestorage capacity, the access time for each cell is also increased, sothat the refreshing rate is decreased, which may result in aninsufficient refreshing of each storage cell.

Moreover, in order to test the memory 10, it is necessary to apply theselection signals S₁ to S_(n) to the memory 10 one by one and to comparethe inputted data with the outputted data for each selection signal.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide asequential-access memory which can have an increased storage capacitywithout decreasing the refreshing rate, thereby enabling the memory tobe refreshed without fail.

It is another object of the invention to provide a sequential-accessmemory which can be tested in a simple manner.

According to an aspect of the present invention, there is provided asequential-access memory comprising at least two memory cell arrays eachof which comprises a plurality of dynamic-type memory cells each havinga write selection line, a read selection line, a data output line and adata input line, the plurality of memory cells being arranged to form arow of memory cells in such a manner that the read selection line ofeach memory cell is connected to the write selection line of the memorycell which comes next to the each memory cell to form an addressselection line, the data output lines of the plurality of memory cellsbeing connected together to form a read data line, the data input linesof the plurality of memory cells being connected together to form a datawrite line; access control means for activating the address selectionlines of each of the at least two memory cell arrays one after anotherat a predetermined time interval; and delay circuit means interposedbetween each adjoining pair of memory cell arrays among the at least twomemory cell arrays to connect the at least two memory arrays in seriesin such a manner that data on the read data line of each memory cellarray is delayed by a predetermined time interval and fed to the writedata line of the memory cell array which comes next to the each memorycell array.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a sequential-access memory of prior art;

FIG. 2 is a time chart of vaiious signals of the sequential-accessmemory of FIG. 1;

FIG. 3 is a block diagram of a sequential-access memory 50 provided inaccordance with one embodiment of the present invention;

FIG. 4 is a circuit diagram of a part of the memory 50 of FIG. 3;

FIG. 5 is a circuit diagram of one of the memory cells SC₁ to SC₄₅ ofthe memory cell arrays 51 and 52 of FIG. 4;

FIG. 6 is a detailed block diagram of the logic circuit 60 of the memory50 of FIG. 3;

FIG. 7 is a timing chart showing the sequence of selection of the memorycells SC₁ to SC₄₅ of the memory cell arrays 51 and 52; and

FIG. 8 is the continuation of the timing chart of FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

The present invention will now be described with reference to theaccompanying drawings.

Referring now to FIG. 3, there is shown a sequential-access memory 50provided in accordance with one embodiment of the present inventionwhich includes two storage sections RAM1 and RAM2 serially connected toeach other. This sequentialaccess memory 50 is operated in accordancewith a pair of clock signals φ1 and φ2 which are 180° out of phase fromeach other. The storage sections RAM and RAM2 comprise dynamic storagecell arrays 51 and 52, respectively, each of which includes 24 rows by45 columns dynamic storage cells. In this case, each column of cellsstore one word of data which is composed of 24 bits, and each row ofcells are composed, as shown in FIG. 4, of 45 dynamic storage cells SC₁to SC₄₅ which are serially connected in a manner described above for thememory 10 of FIG. 1.

As shown in FIG. 5, each cell SC_(i) ("i" is any one of "1" to "45") iscomposed of a conventional three-transistor type dynamic RAM storagecell which comprises, similarly to the cell 11_(i) of FIG. 1, threetransistors T3 to T5 and a capacitor C. The transistor T4 cooperateswith the capacitor C to form a memory element, wherein the electriccharge of the capacitor C determines the ON/OFF state of the transistorT4. The transistor T5 of the cell SC_(i) is brought into the ON state toconnect the transistor T4 to a read data line RL when a "1" signal isapplied to a read selection line R_(i) which is connected to a gate ofthe transistor T5. On the other hand, the transistor T3 is brought intothe ON state to connect a write data line WL to the capacitor C (or agate of the transistor T4), when a "1" signal is applied to a writeselection line W_(i) which is connected to a gate of the transistor T3.

The cells SC₁ to SC₄₅ of each row are connected, as shown in FIG. 4,such that the write selection line W_(i) of the cell SC_(i) is connectedto the read selection line R_(i+1) of the succeeding stage cellSC_(i+1). The read selection lines R₁ to R₄₅ are supplied respectivelywith selection signals S₁ to S₄₅. More specifically, a junction point ofthe write selection line W₁ of the cell SC₁ and the read selection lineR₂ of the cell SC₂ is supplied with the selection signal S₂, a junctionpoint of the write selection line W₂ of the cell SC₂ and the readselection line R₃ of the cell SC₃ is supplied with the selection signalS₃, and so on. A junction point of the write selection line W₄₅ of thecell SC₄₅ and the read selection line R₁ of the cell SC₁ is suppliedwith the selection signal S₁. All the transistors T3 of the cells SC₁ toSC₄₅ are connected to the write data line WL, and all the transistors T5of the cells SC₁ to SC₄₅ are connected to the read data line RL. Theselection signals S₁ to S₄₅ are rendered "1" one after another insynchronization with the clock φ2, in a manner described above for thememory 10 of FIG. 1 (see FIG. 2), to sequentially access the cells SC₁to SC₄₅.

With this arrangement, when the selection signals S₁ to S₄₅ are rendered"1" one after another, data are sequentially read from the cells SC₁ toSC₄₅ and outputted onto the read data line RL as read data DR. Inparallel with this, write data DW on the write data line WL aresequentially written into the cells SC₄₅ and the cells SC₁ to SC₄₄. Theabove operation is repeatedly carried out.

Each data DR outputted onto the read data line RL is supplied to a latch46 provided in a delay circuit 53 and stored thereinto by the clocksignal φ2 which is generated simultaneously with the selection signal Sby which the data DR was read. The data DR thus held by the latch 46 isthen stored into a delay circuit element 47 by the clock signal φ1 whichis generated immediately after the clock signal φ2 which caused the dataDR to be stored in the latch 46. This data DR is outputted from thedelay circuit element 47 by the clock signal φ2 which comes next to theclock signal φ1 which caused the data DR to be stored in this delaycircuit element 47. Thus, the delay circuit element 47 delays the dataDR by a time period T equal to one cycle of the clock signal φ2, thatis, a time interval at which the selection signals S are generated. Thedata outputted from the delay circuit element 47 is outputted through anamplifier 48.

The read data line RL of the row of cells SC₁ to SC₄₅ is connected to atransistor 49 which conducts to pre-charge the read data line RL inresponse to a pre-charge control pulse signal PC applied to a gate ofthe transistor 49. The precharge control pulse signal PC is generated insynchronization with the clock signal φ1 (see FIG. 2).

The left-hand side circuit portion of FIG. 4 which includes the cellsSC₁ to SC₄₅ and the transistor 49 constitute one of the first to 24throws of cells of the cell array 51 (or cell array 52) shown in FIG. 3,and the righthand side circuit portion of FIG. 4 which includes thelatch 46, the delay circuit element 47 and the amplifier 48 constituteone of 24 circuit portions of the delay circuit 53 (or 54) which areprovided correspondingly to the first to 24th rows of cells of the cellarray 51 (or 52). Thus, the number of read data lines RL, which connectthe cell array 51 to the delay circuit 53 (or the cell array 52 to thedelay circuit 54) is 24. The first to 24th read data lines RL of thecell array 51 are connected through the corresponding circuit portionsof the delay circuit 53 to the first to 24th write data lines WL of thecell array 52, respectively, as shown in FIG. 3.

The cell arrays 51 and 52 are provided respectively withsequential-access control circuits 55 and 56 each of which causes theselection signals S₁ to S₄₅ to become "1" one after another inaccordance with 6-bit output of a delay circuit 57. The delay circuit 57is arranged to delay a 6-bit count output of a modulo-45 counter 58 bythe time period T equal to one cycle of the clock signal φ2 (or clocksignal φ1). The counter 58 counts the pulses of the clock signal φ2 tooutput the 6-bit count output which is stored into the delay circuit 57by the next clock φ1. The count output of the counter 58 stored in thedelay circuit 57 is outputted therefrom by the next clock signal φ2.Thus, as the counter outputs "0", "1", "2", "3", "4". . . "43", "44","0", "1". . . as its count output, each of the sequential-access controlcircuits 55 and 56 renders the selection signals S₁, S₂, S₃, S₄, S₅, . .. S₄₄, S₄₅, S₁, S₂. . . "1" one after another. The sequential-accesscontrol circuit 55 (56) may comprise a decoder and and a shift register,and the structure thereof is within the skill of one of ordinary skillin the art.

Thus, the storage section RAM1, which comprises the cell array 51 having24 rows by 45 columns of cells and the sequential-access control circuit55, is serially connected through the delay circuit 53 to the storagesection RAM2 which comprises the cell array 52 having 25 rows by 45columns of cells and the sequential-access control circuit 56. Both ofthe storage sections RAM1 and RAM2 thus connected in series aresimultaneously accessed by the sequential-access control circuits 55 and56.

The 24-bit read data DR on the first to 24th read data lines RL of thecell array 52 are delayed by the delay circuit 54 by the time period Tequal to one cycle of the clock signal φ2 (or φ1), and supplied as24-bit data Da to a first data input terminal of a logic circuit 60. Thelogic circuit 60 subjects the 24-bit data Da fed from the delay circuit54 and 24-bit data Db fed from an exterior circuit (not shown) to apredetermined operation, and outputs the operation result as data Dc.

The structure of the logic circuit 60 will now be more fully describedwith reference to FIG. 6

In FIG. 6, each of the data Da and Db is divided into six series of4-bit data to effect the predetermined operation (an addition operationin this case) on the pair of data of each series. More specifically, thelowest-order four bits of each of the data Da and Db are supplied to thefirst series operation circuit 61, the second lowest-order four bits ofeach of the data Da and Db are supplied to the second series operationcircuit 62, . . . and the highest-order four bits of each of the data Daand Db are supplied to the sixth series opertion circuit 66.

The first series operation circuit 61 comprises a fourbit full adder 61₁for adding the lowest-order four bits of the data Da and Db together,and serially connected six delay circuits 61₂ to 61₇ each responsive tothe clock signals φ2 and φ1 for delaying four-bit data inputted theretoby the time period T corresponding to one cycle of the clock signal φ2(or φ1). Since the adder 61₁ is disposed foremost of all, the four-bitaddition result outputted from the adder 61₁ is delayed by a time periodequal to 6T and supplied to input terminals of the storage section RAM1,that is to say, to the first to fourth write data lines WL of the cellarray 51. A carry output c1 of the adder 61₁ is supplied to a delaycircuit 61₈ which delays this carry c1 in response to the clock signalsφ2 and φ1 by the time period T equal to one cycle of the clock signal φ2(or φ1), and supplies the delayed carry c1 to the second seriesoperation circuit 62.

The second series operation circuit 62 comprises a eightbit delaycircuit 62₁ for delaying the second lowest-order four bits of each ofthe data Da and Db by the time period equal to T, a full adder 62₂ foradding the two four-bit data outputted from the delay circuit 62₁ andthe delayed carry c1 together, and serially connected five delaycircuits 62₃ to 62₇ eaoh for delaying a four-bit input data by the timeperiod equal to T. Thus, the second lowest-order four bits of the dataDa and Db are first delayed by the time period T and then added togetherwith the delayed carry c1 from the first series operation circuit 61.The four-bit addition result is subsequently delayed by a time periodequal to 5T and supplied to the fifth to eighth write data lines WL ofthe cell array 51. A carry output c2 of the adder 62₂ is delayed by thetime period equal to T by a delay circuit 62₈ and supplied to the thirdseries operation circuit 63.

The third series operation circuit 63 comprises two eight-bit delaycircuits 63₁ and 63₂ for delaying the third lowest-order four bits ofeach of the data Da and Db by a time period equal to 2T, a full adder63₃ for adding the two four-bit data outputted from the delay circuit63₂ and the delayed carry c2 together, and serially connected four delaycircuits 63₄ to 63₇ each for delaying a four-bit input data by the timeperiod equal to T. Thus, the third lowest-order four bits of the data Daand Db are first delayed by the time period 2T and then added togetherwith the delayed carry c2 from the second series operation circuit 62.The four-bit addition result is subsequently delayed by a time periodequal to 4T and supplied to the ninth to twelfth write data lines WL ofthe cell array 51. A carry output c3 of the adder 63₃ is delayed by thetime period equal to T by a delay circuit 63₈ and supplied to the fourthseries operation circuit 64.

Similarly, the fourth, fifth and sixth series operation circuits 64, 65and 66 have three, four and five delay circuits upstream of their fulladders 64₄, 65₅ and 66₆, respectively, so that addition operations areeffected in the circuits 64, 65 and 66 at timings the time period Tshifted from each other. The addition results outputted from the adders64₄, 65₅ and 66₆ are delayed, before being outputted from this logiccircuit 60, respectively by three delay circuits, two delay circuits andone delay circuit each for delaying its input data by the time periodequal to T. A carry output c4 of the adder 64₄ is supplied to the adder65₅ through a delay circuit 64₈, and a carry output c5 of the adder 65₅is supplied through a delay circuit 65₈ to the adder 66₆.

With this logic circuit 60, one of the pairs of four-bit portions of thedata Da and Db are added together within one clock period T, so that allthe 24 bits of the data Da and those of the data Db are added togetherwithin six clock periods 6T. In this case, since each full adder is offour-bit type, the addition of the two data Da and Db is performed at ahigh speed.

Thus, the 24-bit data Da outputted from the delay circuit 54 (FIG. 3) isadded to the 24-bit data Db fed from the external circuit, and the24-bit data Dc obtained as a result of the addition is supplied to thefirst to 24th write data lines WL of the cell array 51 six clock periods6T later.

The operation of the memory 50 will no be described with reference toFIGS. 7 and 8.

FIGS. 7 and 8 are time charts wherein the horizontal axes represent timeand wherein the numbers of the cells simultaneously accessed by eachselection signal S are indicated along the vertical axes. For example,at time t₁ of FIG. 7, the selection signals S₂ of "1" are applied to thewrite selection lines W₁ and the read selection lines R₂ of the storagesection RAM1 and to the write selection lines W₁ and the read selectionlines R₂ of the storage section RAM2. As a result, data are writtenrespectively into the first cells SC₁ of the storage sections RAM1 andRAM2, and at the same time data are read respectively from the secondcells SC₂ of the storage sections RAM1 and RAM2. Each of FIGS. 7 and 8is divided into upper and lower parts, wherein the lower part is thecontinuation of the upper part. Also, the upper part of FIG. 8 is thecontinuation of the lower part of FIG. 7.

At time t₂ of FIG. 7, which is one clock period T after the time t₁, theselection signals S₃ are rendered "1", and as a result, data are writteninto the second cells SC₂ of the storage sections RAM1 and RAM2, and atthe same time data are read from the third cells SC₃ of the storagesections RAM1 and RAM2. In this manner, the selection signals S₁ to S₄₅are rendered "1" one after another at a time interval equal to one clockperiod T, so that a round of accesses to all the memory cells of each ofthe storage sections RAM1 and RAM2 are performed within 45 clock periods45T.

Data written into the first cells SC₁ of the storage section RAM1 by theselection signal S₂ at the time t₁ is read from the same cells SC₁ bythe selection signal S₁ forty four (44) clock periods later, that is, attime t₃ (=t₁ +44T). The data thus read from the cells SC₁ at the time t₃is held by the latches 46 of the delay circuit 53 and written, by theselection signal S₂, into the first cells SC₁ of the storage sectionRAM2 through the delay circuit elements 47 forty five (45) clock periodsafter the time t₁, that is, at time t₄ (=t₁ +45T).

The data written into the first cells SC₁ of the storage section RAM2 atthe time t₄ is read from the same cells SC₁ forty four clock periodslater, that is, at time t₅ (=t.sub. +44T). The data thus read from thecells SC₁ at the time t₅ is held by the latches 46 of the delay circuit54 and supplied through the delay circuit elements 47 to the inputterminal of the logic circuit 60 as the data Da forty five (45) clockperiods after the time t₄, that is, at time t₆ (=t₄ +45T).

The foregoing is the process of the data written into the first cellsSC₁ of the storage section RAM1. The same is true of each of datawritten into other cells. More specifically, data written into eachcolumn of cells (i. e., the cells SC₁, the cells SC₂, . . . or the cellsSC₄₅) of the storage section RAM1 is outputted from the storage sectionRAM2 ninety clock periods (90T) later and supplied to the input terminalof the logic circuit 60. In other words, the sequential-access memory 50comprising the storage sections RAM1 and RAM2 serves as a delay circuithaving a delay time equal to ninety clock periods.

The data Da supplied to the logic circuit 60 at the time t₆ is added tothe data Db fed to the logic circuit 60 at that time from the externalcircuit, and outputted from the logic circuit 60 as the data Dc sixclock periods later, that is, at time t₇. The data Dc thus outputtedfrom the logic circuit 60 at the time t₇ is written into the seventhcells SC₇ of the (storage section RAM1 (see FIGS. 7-(b), 7-(g) and7-(h)). More specifically, each of the data Da and Db is divided intothe six series of four-bit data in the logic circuit 60, and the pairsof series of four-bit data are added together in sequence from the paircorresponding to the lowest-order four bits of the data Da and Db. Theresults of these additions in the form of 24-bit data (or the data Dc)are simultaneously outputted from the logic circuit 60 six clock periodslater, and written into the seventh cells SC₇ (24 bits) of the storagesection RAM1.

Thus, the data read from the first cells SC₁ of the storage section RAM1at the time t₁ reaches the seventh cells SC₇ of the same storage sectionRAM1 ninety six (96) clock periods after the time t₁, that is at thetime t₇. In this case, the data Da is added to the data Db while beingdelayed.

Thus, each of the storage sections RAM1 and RAM2 operates in a cyclecorresponding to 45 clock periods, but the memory 50 operates as a whole(inclusively of the logic circuit 60) in a cycle corresponding to 96clock periods. Therefore, the data written into the first cells SC₁ ofthe storage section RAM1 at the time t₁ in the first phase I shown inFIG. 7 is inputted to the logic circuit 60 at the time t₆ which is 90clock periods after the time t₁. After making a full round in the entirecircuit of the memory 50, the data is written into the seventh cells SC₇of the storage section RAM1 96 clock periods after the time t₁, that is,at the time t₇ in the beginning of the second phase II shown in FIG. 7.After making the second round in the entire circuit of the memory 50,the same data is written into the thirteenth cells SC₁₃ of the storagesection RAM1 90 clock periods after the time t₇ in the third phase IIIshown in FIG. 8. After the third round, that is, 288 clock periodslater, the data is stored in the nineteenth cells SC₁₉ of the storagesection RAM1. The data is thereafter written into the 25th cells SC₂₅,31st cells SC₃₁, the 37th cells SC₃₇, and so on. Thus, each time a roundof the data in the circuit is made, the data is stored in those cells ofthe storage section RAM1 which are disposed six cells downstream of thecells into which the same data was precedingly written.

Thus, with the arrangement of the memory 50, an access to the cells isindependently performed in each of the storage sections RAM1 and RAM2.In each of the storage sections RAM1 and RAM2, accesses to all thecolumns of cells are performed every 45 clock periods, so that thestorage capacity of the memory can be increased two times larger thanthe memory 10 of FIG. 1 with the refreshing cycle of each cell beingkept at 45 clock periods.

In the case of the data Db being "0", data composed of 24 "1" bitswritten into the first cells SC₁ of t section RAM1 is transferred insequence from the first cells SC₁ to the seventh cells SC₇, from theseventh cells SC₇ to the thirteenth cells SC₁₃, from the thirteenthcells SC₁₃ to the nineteenth cells SC₁₉, from the nineteenth cells SC₁₉to the twenty-fifth cells SC₂₅, and so on every 96 clock periods.Therefore, the operation of the cells SC₁, SC₇, SC₁₃, and so on can beexamined by monitoring the output data Dc of the logic circuit 60 every96 clock periods.

Thus, with the arrangement of the memory 50, the procedures of test ofthe operation thereof can be significantly simplified in comparison withthe memory 10 wherein writing of data and reading of data must beperformed with respect to each of the selection lines. In the case wherethe logic circuit 60 is replaced with a circuit having a delay timeequal to one clock period, data written into the first cells SC₁ istransferred in sequence from the first cells SC₁ to the second cellsSC₂, from the second cells SC₂ to the third cells SC₃, from the thirdcells SC₃ to the fourth cells SC₄, from the fourth cells SC₄ to thefifth cells SC₅, and so on each time the data makes a round in thecircuit. Therefore, only one time of writing of data is needed to testall the cells, whereby the test procedures are remarkably simplified.

In addition, each of the cells SC₁ to SC₄₅ comprises only threetransistors, so that the power and space required can be substantiallysaved.

Although the above-described memory 50 comprises only two sets ofstorage sections RAM1 and RAM2 serially connected to each other, it willbe evident that the number of sets of storage sections to be seriallyconnected may be increased to augment the storage capacity with therefresh period being kept short. It will also be appreciated that thenumber of cells of each row should not necessarily be restricted to 45and that the number may be set to a desired value within the rangewherein the cells of each storage section can be properly refreshed.Furthermore, the delay time of the logic circuit 60 may be set to adesired value within a certain range.

With the arrangement of the above-described memory 50, the number ofbits of one data which can be written into or read from the storagesection by one access is 24. However, the memory 50 may be modified sothat the number of bits of one data is greater than 24 and that anotherlogic circuit having a function different from that of the logic circuit60 is additionally provided. In this case, the sequential-access controlcircuits need not be additionally provided.

What is claimed is:
 1. A sequential-access memory comprising:(a) aplurality of memory cell arrays arranged so that at least two memorycell arrays are adjoining, each memory cell array comprising a pluralityof dynamic-type memory cells each having a write selection line, a readselection line, a data output line and a data input line, said pluralityof memory cells being arranged to form at least one row of memory cellsin such a manner that the read selection line of each memory cell isconnected to the write selection line of the memory cell which comesnext to said each memory cell to form an address selection line, thedata output lines of said plurality of memory cells being connectedtogether to form a read data line, said data input lines of saidplurality of memory cells being connected together to form a write dataline; (b) access control means for activating the address selectionlines of each of said memory cell arrays one after another at apredetermined time interval; and (c) delay circuit means interposedbetween each adjoining pair of memory cell arrays among said memory cellarrays to connect said memory arrays in series in such a manner thandata on said read data line of each memory cell array is delayed by apredetermined time interval and fed to said write data line of thememory cell array which comes next to said each memory cell array, thedata on said read data line not being fed from said delay circuit meansback to said each memory cell array.
 2. A sequential-access memorycomprising:(a) a plurality of memory cell arrays arranged so that atleast two memory cell arrays are adjoining, each memory cell arraycomprising a plurality of dynamic-type memory cells each having a writeselection line, a read selection line, a data output line and a datainput line, said plurality of memory cells being arranged to form atleast one row of memory cells in such a manner that the read selectionline of each memory cell is connected to the write selection line of thememory cell which comes next to said each memory cell to form an addressselection line, the data output lines of said plurality of memory cellsbeing connected together to form a read data line, said data input inesof said plurality of memory cells being connected together to form awrite data line; (b) access control means for activating the addressselection lines of each of said memory cell arrays one after another ata predetermined time interval; and (c) delay circuit means interposedbetween each adjoining pair of memory cell arrays among said memory cellarrays to connect said memory arrays in series in such a manner thandata on said read data line of each memory cell array is delayed by apredetermined time interval and fed to said write data line of thememory cell array which comes next to said each memory cell array; eachof said memory cell arrays further comprising least one additional rowof memory cells each identical in structure to said at least one row ofmemory cells, said address selection lines of said at least one row ofmemory cells being connected respectively to the corresponding addressselection lines of said additional row of memory cells, said delaycircuit means delaying data fed from said read data lines of each memorycell array by said predetermined time interval and feeding to said writedata ines of the memory cell array which comes next to said each memorycell array.
 3. A sequential-access memory according to claim 2, whereinone of said delay circuit means comprises a logic circuit for subjectingdata inputted from the read data lines of the memory cell arrayconnected to input side of said one delay circuit means to apredetermined operation and for outputting data representative of theresult of said predetermine operation to the write data lines of thememory cell array connected to output side of said one delay circuitmeans in a delayed relation by a predetermined time period to saidinputted data.
 4. A sequential-access memory according to claim 3,wherein said predetermined operation effected by said logic circuit isan addition of said inputted data to data fed from an external circuit.